Abstract
While the fetch unit has been identified as one of the major bottle-necks of Simultaneous Multithreading architecture, several fetch schemes were proposed by prior works to enhance the fetching efficiency. Among these schemes, ICOUNT, proposed by Tullsen et al. were considered to be a great scheme. The ICOUNT scheme works mainly because it favors the thread which fast moving through the pipeline, thus use the resource effectively. We think it is better letting the thread which tends to have more long latency instructions to get the priority at adequate time since long latency instructions are very likely on program’s critical path. We proposed a dynamic fetch scheme which gives the long latency bound thread higher priority while the RUU or LSQ is under low usage. Our motivation is to gain further performance by not only use the resource effectively but also by the urgency of the instructions.
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References
Dorai, G., Yeung, D.: Transparent threads: resource sharing in SMT processors for high single-thread performance. In: 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), September 22-25 (2002)
Eggers, S., Emer, J., Levy, H., Lo, J., Stamm, R., Tullsen, D.: Simultaneous multi-threading: A platform for next-generation processors. Technical Report TR-97-04-02, Uni¬versity of Washington, Department of Computer Science and Engineering (April 1997)
El-Moursy, A., Albonesi, D.: Front-end policies for improved issue efficiency in SMT processors. In: 9th International Symposium on High-Performance Computer Architecture, February 2003, pp. 31–40 (2003)
Hirata, H., Kimura, K., Nagamine, S., Mochizuki, Y., Nishimura, A., Nakase, Y., Nishi-zawa, T.: An elementary processor architecture with simultaneous instruction issuing from multiple threads. In: 19th Annual International Symposium on Computer Architecture, May 1992, pp. 136–145 (1992)
Knijnenburg, P.M.W., Ramirez, A., Latorre, F., Larriba, J., Valero, M.: Branch classification to control instruction fetch in simultaneous multithreaded architectures. In: International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA 2002), January 10-11 (2002)
Lo, J., Eggers, S., Emer, J., Levy, H., Stamm, R., Tullsen, D.: Converting thread-level parallelism into instruction-Level parallelism via simultaneous multithreading. In: ACM Transactions on Computer Systems, August 1997, pp. 322–354 (1997)
Luo, K., Franklin, M., Mukherjee, S., Sezne, A.: Boosting SMT performance by specula¬tion control. In: 15th Proceedings of International Parallel and Distributed Processing Symposium, IPDPS (2001)
Madon, D., Sanchez, E., Monnier, S.: A Study of a Simultaneous Multithreaded Architecture. In: Amestoy, P.R., Berger, P., Daydé, M., Duff, I.S., Frayssé, V., Giraud, L., Ruiz, D. (eds.) Euro-Par 1999. LNCS, vol. 1685, pp. 716–726. Springer, Heidelberg (1999)
Marr, D., Binns, F., Hill, D., Hinton, G., Koufaty, D., Miller, J., Upton, M.: Hyper-threading technology architecture and microarchitecture. Intel Technology Journal, 4–15 (February 2002)
Tullsen, D., Eggers, S., Emer, J., Levy, H., Lo, J., Stamm, R.: Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In: 23rd Annul International Symposium on Computer Architecture (May 1996)
Tullsen, D., Brown, J.: Handling long-latency loads in a simultaneous multithreading processor. In: 34th Annual International Symposium on Microarchitecture (December 2001)
Tullsen, D., Eggers, S., Levy, H.: Simultaneous multithreading: Maximizing on-chip parallelism. In: 22nd Annul International Symposium on Computer Architecture (June 1995)
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Yang, TR., Shieh, JJ. (2004). Dynamic Fetch Engine for Simultaneous Multithreaded Processors. In: Yew, PC., Xue, J. (eds) Advances in Computer Systems Architecture. ACSAC 2004. Lecture Notes in Computer Science, vol 3189. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30102-8_41
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DOI: https://doi.org/10.1007/978-3-540-30102-8_41
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