Abstract
In today’s superscalar processors, the register renaming scheme is widely used to resolve data dependence constraints. The drawback of the conventional design is that the bit-line load of the storage cell is so heavy that the access time to these storage elements is more than one cycle, impacting the IPC adversely. Moreover, in order to implement precise exception handling, the conventional allocation and recovery strategy is very complex. A novel Rename Register architecture is presented in this paper to overcome these problems. This Rename Register has such features: 1) each storage cell has just one write port, which reduces the bit line load and simplifies the circuit design, so the access time of this Rename Register could be greatly improved; 2) the allocation and recovery strategy of this Rename Register is low-complex. This feature not only simplifies the Rename Register control circuit, but also improves the exception handling speed.
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© 2004 Springer-Verlag Berlin Heidelberg
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Liu, Z., Qi, J. (2004). A Novel Rename Register Architecture and Performance Analysis. In: Yew, PC., Xue, J. (eds) Advances in Computer Systems Architecture. ACSAC 2004. Lecture Notes in Computer Science, vol 3189. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30102-8_42
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DOI: https://doi.org/10.1007/978-3-540-30102-8_42
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23003-8
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