Abstract
One newly designed hierarchical cache scheme is presented in this article. It is a two-level cache architecture using a RAM of a few megabytes and a large pagefile. Majority of cached data is in the pagefile that is nonvolatile and has better IO performance than that of normal data disks because of different data sizes and different access methods used. The RAM cache collects small writes first and then transfers them to the pagefile sequentially in large sizes. When the system is idle, data will be destaged from the pagefile to data disks. We have implemented the hierarchical cache as a filter driver that can be loaded onto the current Windows 2000/Windows XP operating system transparently. Benchmark test results show that the cache system can improve IO performance dramatically for small writes.
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Liu, Rf., Xie, Cs., Tan, Zh., Yang, Q. (2004). A New Hierarchy Cache Scheme Using RAM and Pagefile. In: Yew, PC., Xue, J. (eds) Advances in Computer Systems Architecture. ACSAC 2004. Lecture Notes in Computer Science, vol 3189. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30102-8_43
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DOI: https://doi.org/10.1007/978-3-540-30102-8_43
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