Abstract
In this paper, we propose a timing analysis approach for preemptive multi-tasking real-time systems with caches. The approach focuses on the cache reload overhead caused by preemptions. The Worst Case Response Time (WCRT) of each task is estimated by incorporating cache reload overhead. After acquiring the WCRT of each task, we can further analyze the schedulability of the system. Four sets of applications are used to exhibit the performance of our approach. The experimental results show that our approach can reduce the estimate of WCRT up to 44% over prior state-of-the-art.
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References
Tan, Y., Mooney, V.: Timing Analysis for Preemptive Multi-tasking Real-Time Systems. In: Proceedings of Design, Automation and Test in Europe (DATE 2004), February 2004, pp. 1034–1039 (2004)
Tan, Y., Mooney, V.: Timing Analysis for Preemptive Multi-tasking Real-time Systems with Caches. Technical Report, GIT-CC-04-02, Georgia Institute of Technology (February 2004)
Kirk, D.: SMART (Strategic Memory Allocation for Real-Time) Cache Design. In: Proceedings of IEEE 10th Real-Time System Symposium, December 1989, pp. 229–237 (1989)
Suh, G., Rudolph, L., Devadas, S.: Dynamic Cache Partitioning for Simultaneous Multithreading Systems. In: Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, September 2001, pp. 116–127 (2001)
Liedtke, J., Härtig, H., Hohmuth, M.: OS-Controlled Cache Predictability for Real-Time Systems. In: Proceedings of the Third IEEE Real-Time Technology and Applications Symposium (RTAS 1997), June 1997, pp. 213–227 (1997)
Muller, F.: Compiler Support for Software-based Cache Partitioning. In: Proceedings of ACM SIGPLAN Workshop on Languages, Compliers and Tools for Real-Time Systems, June 1995, pp. 125–133 (1995)
Li, Y., Malik, S.: Performance Analysis of Real-Time Embedded Software. Kluwer Academic Publishers, Boston (1999)
Wolf, F.: Behavioral Intervals in Embedded Software. Kluwer Academic Publishers, Norwell (2002)
Negi, H., Mitra, T., Roychoudhury, A.: Accurate Estimation of Cache-related Preemption Delay. In: Proceedings of ACM Joint Symposium CODES+ISSS, October 2003, pp. 201–206 (2003)
Tomiyama, H., Dutt, N.: Program path analysis to bound cache-related preemption delay in preemptive real-time systems. In: Proceedings of the Eighth International Workshop on Hardware/software Codesign, May 2000, pp. 67–71 (2000)
Ferdinand, C., Heckmann, R., Langenbach, M., Martin, F., Schmidt, M., Theiling, H., Thesing, S., Wilhelm, R.: Reliable and Precise WCET Determination for a Real-Life Processor. In: Henzinger, T.A., Kirsch, C.M. (eds.) EMSOFT 2001. LNCS, vol. 2211, pp. 469–485. Springer, Heidelberg (2001)
Alt, M., Ferdinand, C., Martin, F., Wilhelm, R.: Cache behavior prediction by abstract interpretation. In: Cousot, R., Schmidt, D.A. (eds.) SAS 1996. LNCS, vol. 1145, pp. 52–66. Springer, Heidelberg (1996)
Lundqvist, T., Stenstrom, P.: An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution. Real-Time Systems 17(2-3), 183–207 (1999)
Lehoczky, J., Sha, L., Ding, Y.: The Rate Monotonic Scheduling Algorithm: Exact Characterization and Average Case Behavior. In: Proc. IEEE 10th Real-Time System Symposium, pp. 166–171 (1989)
Liu, C., Layland, J.: Scheduling Algorithms for Multiprogramming in a Hard Real-Time Environment. Journal of ACM 20(1), 26–61 (1973)
Tindell, K., Burns, A., Wellings, A.: An Extendible Approach for Analyzing Fixed Priority Hard Real-Time Tasks. Real-Time Systems 6(2), 133–151 (1994)
Busquets-Mataix, J., Serrano, J., Ors, R., Gil, P., Wellings, A.: Adding instruction cache effect to schedulability analysis of preemptive real-time systems. In: Real-Time Technology and Applications Symposium, June 1996, pp. 204–212 (1996)
Lee, C., Hahn, J., Seo, Y., Min, S., Ha, R., Hong, S., Park, C., Lee, M., Kim, C.: Analysis of Cache-related Preemption Delay in Fixed-priority Preemptive Scheduling. IEEE Transactions on Computers 47(6), 700–713 (1998)
Lee, C., Hahn, J., Seo, Y.-M., Min, S., Ha, R., Hong, S., Park, C., Lee, M., Kim, C.: Enhanced Analysis of Cache-related Preemption Delay in Fixed-priority Preemptive Scheduling. In: IEEE Real-Time Systems Symposium, December 1997, pp. 187–198 (1997)
Sun, D., Blough, D., Mooney, V.: Atalanta: A New Multiprocessor RTOS Kernel for System-on-a-Chip Applications. Technical Report GIT-CC-02-19, Georgia Institute of Technology (April 2002)
Mentor Graphics, Seamless Hardware/Software Co-Verification, http://www.mentor.com/seamless/
Mentor Graphics XRAY Debugger, http://www.mentor.com/embedded/xray/
MediaBench, http://cares.icsl.ucla.edu/MediaBench/
Berkeley MPEG2 decoder, http://bmrc.berkeley.edu/frame/research/mpeg/
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Tan, Y., Mooney, V. (2004). Integrated Intra- and Inter-task Cache Analysis for Preemptive Multi-tasking Real-Time Systems. In: Schepers, H. (eds) Software and Compilers for Embedded Systems. SCOPES 2004. Lecture Notes in Computer Science, vol 3199. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30113-4_14
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DOI: https://doi.org/10.1007/978-3-540-30113-4_14
Publisher Name: Springer, Berlin, Heidelberg
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