Abstract
In this paper, a multiplexer-based concept for creating a run-time configurable array of multipliers capable of accommodating different input data word lengths is presented. In our approach, each element of a m 1× m 2 multiplier array is a parallel-parallel multiplier itself, each again comprising a number of basic arithmetic primitive cells and featuring multiplexers as controllable interconnects. Also, we distinguish between multiplier elements for unsigned and signed numbers which differ in algorithm and design. Diverse architectures are being reviewed and an estimate of hardware complexity and area consumption is given.
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Pfänder, O.A., Hacker, R., Pfleiderer, HJ. (2004). A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_103
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DOI: https://doi.org/10.1007/978-3-540-30117-2_103
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22989-6
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