Abstract
Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processors. In this paper, we present a configurable hardware architecture for adaptive processing of noisy signals for target detection based on Constant False Alarm Rate (CFAR) algorithms. The architecture has been designed to deal with parallel/pipeline processing and to be configured for three versions of CFAR algorithms, the Cell-Average, the Max and the Min CFAR. The architecture has been implemented on a Field Programmable Gate Array (FPGA) with a good performance improvement over software implementations. Results are presented and discussed.
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© 2004 Springer-Verlag Berlin Heidelberg
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Torres-Huitzil, C., Cumplido-Parra, R., López-Estrada, S. (2004). Design and Implementation of a CFAR Processor for Target Detection. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_104
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DOI: https://doi.org/10.1007/978-3-540-30117-2_104
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22989-6
Online ISBN: 978-3-540-30117-2
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