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A Parallel FFT Architecture for FPGAs

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Field Programmable Logic and Application (FPL 2004)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3203))

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Abstract

The inclusion of block RAMs and block multipliers in FPGA fabrics has made them more ammenable for implementing the FFT. This paper describes a parallel FFT design suitable for such FPGA implementations. It consists of multiple, parallel pipelines with a front end butterfly-like circuit to preprocess the incoming data and distribute it to the parallel pipelines. Implementation of the parallel FFT on Virtex II shows superlinear speedups for a range of FFT sizes.

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References

  1. Gramam, A., Gupta, A., Karypis, G., Kumar, V.: Introduction to Parallel Computing, 2nd edn. Pearson Education, Harlow (2003)

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Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT, 84602, USA

    Joseph Palmer & Brent Nelson

Authors
  1. Joseph Palmer
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  2. Brent Nelson
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Editor information

Editors and Affiliations

  1. ITIV - Universitaet Karlsruhe (TH),  

    Jürgen Becker

  2. University of Paderborn,  

    Marco Platzner

  3. IMEC, Kapeldreef 75, Leuven, Leuven, Belgium

    Serge Vernalde

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© 2004 Springer-Verlag Berlin Heidelberg

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Palmer, J., Nelson, B. (2004). A Parallel FFT Architecture for FPGAs. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_105

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  • DOI: https://doi.org/10.1007/978-3-540-30117-2_105

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-22989-6

  • Online ISBN: 978-3-540-30117-2

  • eBook Packages: Springer Book Archive

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