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Design and Efficient FPGA Implementation of an RGB to YCrCb Color Space Converter Using Distributed Arithmetic

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3203))

Abstract

This paper presents two novel architectures for efficient implementation of a Color Space Converter (CSC) suitable for Field Programmable Gate Array (FPGAs) and VLSI. The proposed architectures are based on Distributed Arithmetic (DA) ROM accumulator principles. The architectures have been implemented and verified using the Celoxica RC1000-PP FPGA development board. In addition, they are platform independent and have a low latency (8 cycles). The first architecture has a throughput of height, while the second one is fully pipelined and has a throughput of one and capable of sustained data rate of over 234 mega-conversions/seconds.

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References

  1. Gonzalez, R.C., Woods, R.E.: Digital Image Processing, 2nd edn. Prentice Hall Inc., Englewood Cliffs (2002)

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© 2004 Springer-Verlag Berlin Heidelberg

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Bensaali, F., Amira, A. (2004). Design and Efficient FPGA Implementation of an RGB to YCrCb Color Space Converter Using Distributed Arithmetic. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_113

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  • DOI: https://doi.org/10.1007/978-3-540-30117-2_113

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-22989-6

  • Online ISBN: 978-3-540-30117-2

  • eBook Packages: Springer Book Archive

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