Abstract
A method for testability-oriented optimization of sequential circuits implemented using FPGAs with embedded memory is presented. It specifies the content of those memory words which are not defined by the conventional FSM synthesis. The experimental results confirm its effectiveness; for the largest examined circuit, the self-test session required to achieve an acceptable level of fault escapes for the optimized design, obtained using the proposed procedure, is almost 106 times shorter than for the non-optimized design. The proposed method does not involve any extra circuitry or speed degradation. Also, it does not require any extra reconfiguration during self-testing.
This work was supported by the State Committee for Scientific Research of Poland under grant no. 4 T11D 014 24
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Luba, T., Gorski, K., Wronski, L.B.: ROM-based Finite State Machines with PLA address modifiers. In: Proc. European Design Automation Conf., pp. 272–277 (1992)
Cong, J., Yan, K.: Synthesis for FPGAs with Embedded Memory Blocks. In: Proc. Int. Symp. on FPGAs, pp. 75–82 (2000)
Wilton, S.J.E.: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays. IEEE Trans. on CAD 19, 56–68 (2000)
Rawski, M., Luba, T.: FSM Implementation in Embedded Memory Blocks Using Concept of Decomposition. In: Ciazynski, W., et al. (eds.) Programmable Devices and Systems, pp. 291–296. Pergamon - Elsevier Science (2002)
Krasniewski, A.: Design for Application-Dependent Testability of FPGAs. In: Proc. Int’l Workshop on Logic and Architecture Synthesis, pp. 245–254 (1997)
Renovell, M.: Some Aspects of the Test Generation Problem for an Application-Oriented Test of SRAM-Based FPGAs. Journal of Circuits, Systems, and Computers 12, 143–158 (2003)
Quddus, W., Jas, A., Touba, N.A.: Configuration Self-Test in FPGA-Based Reconfigurable Systems. In: Proc. ISCAS 1999, pp. 97–100 (1999)
Harris, I.G., Menon, P.R., Tessier, R.: BIST-Based Delay Path Testing in FPGA Architectures. In: Proc. IEEE Int. Test Conf., pp. 932–938 (2001)
Krasniewski, A.: Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-Based FPGAs. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 616–626. Springer, Heidelberg (2002)
Tahoori, M.B., McCluskey, E.J., Renovell, M., Faure, P.: A Multi-Configuration Strategy for Application Dependent Testing of FPGAs. In: Proc. VLSI Test Symp. (2004)
Krasniewski, A.: Self-Testing of Sequential Circuits Designed for Implementation in FPGAs with Embedded Memory Blocks. In: Proc. IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop, pp. 75–82 (2004)
David, R.: Random Testing of Digital Circuits: Theory and Applications, pp. 135–191. Marcel Dekker, Inc., New York (1998)
Bardell, P.H., McAnney, W.H., Savir, J.: Built-In Test for VLSI: Pseudorandom Techniques, pp. 177–217. J. Wiley & Sons, Inc., Chichester (1987)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Krasniewski, A. (2004). Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_128
Download citation
DOI: https://doi.org/10.1007/978-3-540-30117-2_128
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22989-6
Online ISBN: 978-3-540-30117-2
eBook Packages: Springer Book Archive