Data Reuse in Configurable Architectures with RAM Blocks

Abstract

The heterogeneity of modern con.gurable devices makes the problem of mapping computations to them increasingly complex. Due to the large number of possibilities for partitioning the data among storage modules, these architectures allow for a much richer memory structure. One general goal in managing this memory is to minimize the number of external memory accesses. A classic technique for reducing this number is to keep reusable data as close to the processor as possible. In order to do so one needs to have a good idea as to if and when the data in a speci.c memory location is going to be reused. General compilers are capable of detecting the reuse as well as applying di.erent techniques in order to exploit this reuse. In this paper we describe how to utilize a compiler reuse analysis to map the data to a con.gurable system, aiming at minimizing the number of external memory accesses. Our target architecture is a system with an external memory, a limited number of internal registers, and a .xed number and capacity of internal RAM blocks.