Abstract
In this paper, we propose a string matching method for high-speed multi-stream packet scanning on FPGA. Our algorithm is capable of lightweight switching between streams, and enables easy implementation of multi-stream scanners. Furthermore, our method also enables high throughput. Using Xilinx XC2V6000-6 FPGA, we achieved 32Gbps for a 1000 characters rule set, and 14Gbps for a 2000 characters one. Rules can be updated by reconfiguration, and we implemented a converter that from given rules automatically generates the matching unit.
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Sugawara, Y., Inaba, M., Hiraki, K. (2004). Over 10Gbps String Matching Mechanism for Multi-stream Packet Scanning Systems. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_50
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DOI: https://doi.org/10.1007/978-3-540-30117-2_50
Publisher Name: Springer, Berlin, Heidelberg
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