Abstract
In this paper we describe a parameterizable FPGA-based implementation of a sigma-delta converter used in a 96kHz audio DAC. From specifications of the converter’s input bitwidth and data sampling frequency, VHDL generic parameters are used to automatically generate the required design. The resulting implementation is optimized to use the minimum internal wordlength and number of stages. We prototyped the converter on an FPGA board for verification purposes and the results are presented.
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Cheung, R.C.C., Pun, K.P., Yuen, S.C.L., Tsoi, K.H., Leong, P.H.W.: An FPGA-based Re-configurable 24-bit 96kHz Sigma-Delta Audio DAC. In: FPT 2003, Tokyo, Japan (2003)
Temes, G.C., Shu, S., Schreier, R.: Architecture for Sigma Delta DACs. In: Norsworthy, S.R., et al. (eds.) Delta Sigma Data Converters, IEEE Press, Los Alamitos (1997)
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© 2004 Springer-Verlag Berlin Heidelberg
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Ludewig, R. et al. (2004). IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_54
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DOI: https://doi.org/10.1007/978-3-540-30117-2_54
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22989-6
Online ISBN: 978-3-540-30117-2
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