Abstract
Field-Programmable Gate Arrays (FPGAs) have lately become a popular target for implementing cryptographic block ciphers, as a well-designed FPGA solution can combine some of the algorithmic flexibility and cost efficiency of an equivalent software implementation with throughputs that are comparable to custom ASIC designs. The recently selected Advanced Encryption Standard (AES) is slowly replacing older ciphers as the building block of choice for secure systems and is well suited to an FPGA implementation. In this paper we explore the design decisions that lead to area/delay tradeoffs in a single-core AES FPGA implementation. This work provides a more thorough description of the defining AES hardware characteristics than is currently available in the research literature, along with implementation results that are pareto optimal in terms of throughput, latency, and area efficiency.
This work was supported in part by the National Science Foundation (NSF) under grant CCR-0325207 and also by an NSF graduate research fellowship.
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References
Stallings, W.: Cryptography and Network Security. Prentice Hall, Englewood Cliffs (2003)
Elbirt, A., Yip, W., Chetwynd, B., Paar, C.: An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists. In: Proc. of the Third Advanced Encryption Standard (AES3) Candidate Conference, pp. 13–27 (2000)
Saggese, G.P., Mazzeo, A., Mazzoca, N., Strollo, A.G.M.: An FPGA-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 292–302. Springer, Heidelberg (2003)
Kaps, J.-P., Paar, C.: Fast DES implementation for FPGAs and its application to a universal key-search machine. In: Proc. of the 5th Annual Workshop on Selected Areas in Cryptography (SAC), pp. 234–247 (1998)
Gonzalez, I., Lopez-Budeo, S., Gomez, F.J., Martinez, J.: Using partial reconfiguration in cryptographic applications: an implementation of the IDEA algorithm. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 194–203. Springer, Heidelberg (2003)
Järvinen, K.U., Tommiska, M.T., Skyttä, J.O.: A fully pipelined memoryless 17.8 Gbps AES-128 encryptor. In: Proc. of the Int’l Symposium on Field Programmable Gate Arrays (FPGA), pp. 207–215 (2003)
Helion Technology, Inc. AES Xilinx FPGA core data sheet (2003), available at http://www.heliontech.com
Wollinger, T., Paar, C.: How secure are FPGAs in cryptographic applications? In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 91–100. Springer, Heidelberg (2003)
Dandalis, A., Prasanna, V., Rolim, J.: An adaptive cryptographic engine for IPSec architectures. In: Proc. of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 132–144 (2000)
Daeman, J., Rijmen, V.: The block cipher Rijndael. In: Quisquater, J.-J., Schneier, B. (eds.) CARDIS 1998. LNCS, vol. 1820, pp. 288–296. Springer, Heidelberg (2000)
National Institute of Standards and Technology. Specification for the Advanced Encryption Standard (AES). FIPS PUB 197 (2001), available at http://csrc.nist.gov
Xilinx, Inc. Virtex-II complete data sheet (2003), available at http://www.xilinx.com
Hodjat, A., Verbauwhede, I.: A 21.54 Gbits/s fully pipelined AES processor on FPGA. In: Proc. of the IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM (2004)
Lipmaa, H.: AES implementation speed comparison (2003), available at http://www.tcs.hut.fi/~aes/rijndael.html
Hodjat, A., Verbauwhede, I.: Minimum area cost for a 30 to 70 Gbits/s AES processor. In: Proc. of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 83–88 (2003)
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Zambreno, J., Nguyen, D., Choudhary, A. (2004). Exploring Area/Delay Tradeoffs in an AES FPGA Implementation. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_59
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DOI: https://doi.org/10.1007/978-3-540-30117-2_59
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