Abstract
In this paper, we present a flow for architecting standard cell libraries in nanometer technologies. The proposed approach relies on a Yield Characterization Environment to evaluate a set of manufacturability metrics and analyze multiple design trade-offs. We have identified four classes of manufacturability objectives that we addressed in our standard cell architectures: Average Functional Yield, Functional Yield Consistency, Performance Consistency and Leakage. Cells optimized for different manufacturability objectives present different trade-offs and require different layout architectures. We will show examples of such different trade-offs and architectural requirements and show the impact of adopting high-manufacturability standard cells on product Yields.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Keutzer, K., Kolwicz, K., Lega, M.: Impact of library size on the quality of automated synthesis. In: Proc. of ICCAD, pp. 120–123 (1987)
Scott, K., Keutzer, K.: Improving cell libraries for synthesis. In: Proc. of CICC, pp. 128–131 (1994)
Strojwas, A.J., Director, S.W.: VLSI: linking design and manufacturing. IEEE Spectrum (10), 24–28 (1988)
Nag, P.K., Maly, W.: Hierarchical extraction of critical area for shorts in very large ICs. Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Systems, 19–27 (November 1995)
Heineken, H.T., Maly, W.: Manufacturability analysis environment - MAPEX. In: Proceedings of Custom Integrated Circuits Conference (May 1994)
Ciplickas, D.J., Li, X., Strojwas, A.J.: Predictive yield modeling of VLSIC’s. In: 5th International Workshop on Statistical Metrology, pp. 28–37 (2000)
YRS User’s manual”, PDF Solutions, Inc.
PDF Solutions,Successful Integration of DFM Nanometer Era Design Flows, CICC 2004 (2004) (to be published)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Dragone, N., Quarantelli, M., Bertoletti, M., Guardiani, C. (2004). High Yield Standard Cell Libraries: Optimization and Modeling. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_15
Download citation
DOI: https://doi.org/10.1007/978-3-540-30205-6_15
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
Online ISBN: 978-3-540-30205-6
eBook Packages: Springer Book Archive