Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications

Abstract

Most of today’s wireless systems implement some sort of channel interleaving to minimize burst errors. The interleaver breaks the temporal correlation of successive samples by reshuffling them prior to transmission. In state-of-the-art solutions, this memory intensive operation is both power consuming due to frequent accesses to large memories and area inefficient due to poor memory-reuse. In this paper, we present a cluster-based deinterleaving method which makes a two-level custom memory hierarchy design possible. The access rate to large memories is reduced by performing sub-array deinterleaving inside much smaller memories thereby lowering the energy dissipation significantly. Moreover, this novel approach solves the memory-reuse bottleneck. Costly adaptation buffers become obsolete yielding a scalable, energy- and area-efficient architecture. The high-speed data packet access (HSDPA) defined in 3GPP serves as target application, where energy reductions of up to 60% with negligible logic overhead is observed for STMicroelectronics’ SRAM library in 0.13 μm CMOS technology.