Abstract
This paper presents a methodology and framework to model the behavior of superscalar microprocessors. The simulation is focused on timing analysis and ignores all functional aspects. The methodology also provides a framework for building new simulators for generic architectures. The results obtained show a good accuracy and a satisfactory computational efficiency. Furthermore, the C++ SDK allows rapid development of new processor models making the methodology suitable for design space exploration over new processor architectures.
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Brandolese, C., Fornaciari, W., Salice, F. (2004). Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_26
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DOI: https://doi.org/10.1007/978-3-540-30205-6_26
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
Online ISBN: 978-3-540-30205-6
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