Abstract
In this paper, we present a tool for estimating the activity of asynchronous circuit specifications. This tool is well suited for monitoring how and where the activity is spread in a circuit. The quality and the precision of the results allow the designer to perform optimizations early in the design flow in order to improve the energy consumption and the speed of asynchronous circuits. Based on the TAST profiler, an energy optimization methodology is defined, focusing on micro-architecture decomposition, choice structures unbalancing and channels splitting. All these techniques are illustrated using an example.
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© 2004 Springer-Verlag Berlin Heidelberg
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Slimani, K., Rémond, Y., Sicard, G., Renaudin, M. (2004). TAST Profiler and Low Energy Asynchronous Design Methodology. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_29
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DOI: https://doi.org/10.1007/978-3-540-30205-6_29
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
Online ISBN: 978-3-540-30205-6
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