Abstract
Low-voltage high-density embedded (e-) RAMs, focusing on RAM cells and peripheral circuits, are described. First, challenges and trends in low-voltage e-RAMs are described based on the S/N issue of RAM cells, and leakage and speed-variation issues of peripheral circuits. Next, state-of-the-art low-voltage e-DRAMs and e-SRAMs are investigated, focusing on leakage-reduction circuits. Finally, future prospects for e-RAM cells and peripheral circuits are discussed in terms of low-voltage designs.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Itoh, K.: VLSI Memory Chip Design. Springer, New York (2001)
Nakagome, Y., et al.: Review and prospects of low-voltage RAM circuits. IBM J. R & D 47(5/6), 525–552 (2003)
Kamei, T., et al.: A Resume-Standby Application Processor for 3G Cellular Phones. In: 2004 ISSCC Dig. Tech. Papers, February 2004, pp. 336–337 (2004)
Yamaoka, M., et al.: A 300 MHz 25μA/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor. In: 2004 ISSCC Dig. Tech. Papers, February 2004, pp. 494–495 (2004)
Hardee, K., et al.: A 0.6V 205MHz 19.5ns tRC 16Mb Embedded DRAM. In: 2004 ISSCC Dig. Tech. Papers, February 2004, pp. 494–495 (2004)
Morishita, F., et al.: A 312MHz 16Mb Random-Cycle Embedded DRAM Macro with 73 μW Power-Down Mode for Mobile Applications. In: 2004 ISSCC Dig. Tech. Papers, February 2004, pp. 202–203 (2004)
Yamaoka, M., et al.: Low Power SRAM Menu for SOC Application Using Yin-Yang- Feedback Memory Cell Technology. In: Symp. VLSI Circuits Dig. (June 2004)
Nii, K., et al.: A 90 nm Low Power 32K-Byte Embedded SRAM with Gate Leakage Suppression Circuit for Mobile Applications. In: Symp. VLSI Circuits Dig., June 2003, pp. 247–150 (2003)
Inukai, T., Hiramoto, T.: Suppression of Stand-by Tunnel Current in Ultra-Thin Gate Oxide MOSFETs by Dual Oxide Thickness MTCMOS(DOT-MTCMOS). In: Ext. Abst. 1999 Int’l Conf. SSDM, Tokyo, pp. 264–265 (1999)
Osada, K., et al.: 16.7fA/cell Tunnel-Leakage-Suppressed 16Mb SRAM for Handling Cosmic-Ray-Induced Multi-Errors. In: 2003 ISSCC Dig. Tech. Papers, February 2003, pp. 302–303 (2003)
Noda, H., et al.: A 143MHz 1.1W 4.5Mb Dynamic TCAM with Hierarchical Searching and Shift Redundancy Architecture. In: 2004 ISSCC Dig. Tech. Papers, February 2004, pp. 208–209 (2004)
Nahas, J., et al.: A 4Mb 0.18μm 1T1MTJ Toggle MRAM Memory. In: 2004 ISSCC Dig. Tech. Papers, February 2004, pp. 44–45 (2004)
Cho, W.Y., et al.: A 0.18μm 3.0V 64Mb Non-Volatile Phase-Transition Random-Access Memory(PRAM). In: 2004 ISSCC Dig. Tech. Papers, February 2004, pp. 40–41 (2004)
Nakagome, Y., et al.: Symp. VLSI Circuits Dig., June 1992, pp. 82–83 (1992)
Kawahara, T., et al.: Subthreshold current reduction for decoded-driver by self-reverse biasing. IEEE J. Solid-State Circuits 28, 1136–1144 (1993)
Horiguchi, M., et al.: Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI’s. IEEE J. Solid-State Circuits 28, 1131–1135 (1993)
Sakata, T., et al.: Subthreshold-current reduction circuits for multi-gigabit DRAM’s. IEEE J. Solid-State Circuits 29, 761–769 (1994)
Osada, K., et al.: Universal-Vdd 0.65-2.0V 32 kB Cache using Voltage-Adapted Timing- Generation Scheme and a Lithographical-Symmetric Cell. In: 2001 ISSCC, Dig. Tech. Papers, February 2001, pp. 168–169 (2001)
Itoh, K., et al.: Review and Future Prospects of Low-voltage Embedded RAMs. In: CICC2004 Dig. (October 2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Itoh, K., Osada, K., Kawahara, T. (2004). Low-Voltage Embedded RAMs – Current Status and Future Trends. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_3
Download citation
DOI: https://doi.org/10.1007/978-3-540-30205-6_3
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
Online ISBN: 978-3-540-30205-6
eBook Packages: Springer Book Archive