Abstract
Clustered L0 buffers are an interesting alternative for reducing energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 clusters is performed as an hardware optimization, where the compiler generates a schedule and based on the given schedule L0 clusters are synthesized. The result of clustering is schedule dependent, which offers a design space for exploring the effects on clustering by scheduling. This paper presents a study indicating the potentials offered by shuffling operations within a VLIW instruction on L0 cluster synthesis. The simulation results indicate that potentially up to 75% of L0 buffer energy can be reduced by shuffling operations.
This work is supported in part by MESA under the MEDEA+ program.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Mediabench, http://www.cs.ucla.edu/leec/mediabench
Trimaran: An Infrastructure for Research in Instruction-Level Parallelism (1999), http://www.trimaran.org
Standard Performance Evaluation Corporation: SPEC CPU 2000 (2000), http://www.spec.org
Bajwa, R.S., Hiraki, M., Kojima, H., Gorny, D.J., Nitta, K., Shridhar, A., Seki, K., Sasaki, K.: Instruction buffering to reduce power in processors for signal processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5(4), 417–424 (1997)
Benini, L., Bruni, D., Chinosi, M., Silvano, C., Zaccaria, V.: A power modeling and estimation framework for vliw-based embedded system. ST Journal of System Research 3(1), 110–118 (2002) (Also presented in PATMOS 2001)
Bona, A., Sami, M., Sciuto, D., Zaccaria, V., Silvano, C., Zafalon, R.: An instruction-level methodology for power estimation and optimization of embedded vliw cores. In: Proc of Design Automation and Test in Europe (DATE) (March 2002)
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework for architectural-level power analysis and optimizations. In: Proc of the 27th International Symposium on Computer Architecture (ISCA), June 2000, pp. 83–94 (2000)
Burd, T., Brodersen, R.W.: Energy Efficient Micorprocessor Design, 1st edn. Kluwer Academic Publishers, Dordrecht (January 1992)
Faraboschi, P., Brown, G., Fischer, J., Desoli, G., Homewood, F.: Lx: A technology platform for customizable vliw embedded processing. In: Proc of 27th International Symposium on Computer Architecture (ISCA) (June 2000)
Jacome, M.F., de Veciana, G.: Design challenges for new application-specific processors. Special issue on Design of Embedded Systems in IEEE Design & Test of Computers (April-June 2000)
Jayapala, M., Barat, F., Aa, T.V., Catthoor, F., Deconinck, G., Corporaal, H.: Clustered l0 buffer organization for low energy embedded processors. In: Proc of 1st Workshop on Application Specific Processors (WASP), held in conjunction with MICRO-35 (November 2002)
Jayapala, M., Barat, F., OpDeBeeck, P., Catthoor, F., Deconinck, G., Corporaal, H.: A low energy clustered instruction memory hierarchy for long instruction word processors. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds.) PATMOS 2002. LNCS, vol. 2451, p. 258. Springer, Heidelberg (2002)
Lapinskii, V., Jacome, M.F., de Veciana, G.: Applicationspecific clustered vliw datapaths: Early exploration on a parameterized design space. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 21(8), 889–903 (2002)
Lee, L.H., Moyer, W., Arends, J.: Instruction fetch energy reduction using loop caches for embedded applications with small tight loops. In: Proc of International Symposium on Low Power Electronic Design (ISLPED) (August 1999)
Texas Instruments Inc., TMS320C6000 Power Consumption Summary (November 1999), http://www.ti.com
Texas Instruments Inc, TMS320C6000 CPU and Instruction Set Reference Guide (October 2000), http://www.ti.com
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Jayapala, M., Aa, T.V., Barat, F., Catthoor, F., Corporaal, H., Deconinck, G. (2004). L0 Cluster Synthesis and Operation Shuffling. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_33
Download citation
DOI: https://doi.org/10.1007/978-3-540-30205-6_33
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
Online ISBN: 978-3-540-30205-6
eBook Packages: Springer Book Archive