Abstract
A 32-bit ALU has been implemented in the baseline Philips-Motorola-ST 0.10um triple-VT CMOS technology. The ALU core has been designed with a combined dynamic/static design approach aiming at high-speed operation and standard cells based design. It runs at frequencies ranging from 3.8 GHz to 5.4 GHz (with nominal supply at room temperature) depending on the actual fabrication process corner.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Han, T., Carlson, D.A.: Fast Area Efficient VLSI Adders. In: 8th Symposium on Computer Arithmetic, May 1987, pp. 49–56 (1987)
Bai, X., et al.: Uncertainty-aware circuit tuning. In: Proc. of 39th Design Automation Conference, New Orleans (June 2002)
Kogge, P.M., Stone, H.S.: A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations. IEEE Transactions on Computers 22(8), 786–793 (1973)
Anders, M., et al.: A 6.5GHz 130nm Single-Ended Dynamic ALU and Instruction- Scheduler Loop. In: ISSCC Digest of Technical Papers, February 2002, pp. 410–477 (2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Pessolano, F., Meijer, R.I.M.P. (2004). A 260ps Quasi-static ALU in 90nm CMOS. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_39
Download citation
DOI: https://doi.org/10.1007/978-3-540-30205-6_39
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
Online ISBN: 978-3-540-30205-6
eBook Packages: Springer Book Archive