Abstract
A novel semi-dynamic level-converting flip-flop is proposed and compared to standard level shifter circuits concerning speed, power, integration and soft-error-rate. The flip-flop operates at one single supply voltage which allows most compact design as well as reduced place and route effort. In addition to its superior delay and power consumption properties, it offers simple implementation of robust multi-vdd low power systems with minimum area overhead and easy integrability into standard design flows.
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© 2004 Springer-Verlag Berlin Heidelberg
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Henzler, S., Georgakos, G., Berthold, J., Schmitt-Landsiedel, D. (2004). Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_41
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DOI: https://doi.org/10.1007/978-3-540-30205-6_41
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
Online ISBN: 978-3-540-30205-6
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