Abstract
Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on-chip buses implemented in Ultra Deep Submicron CMOS technology. Elimination or minimization of crosstalk is crucial to the performance and reliability of SoC designs. This paper presents a novel on-chip bus encoding scheme targeting high performance generic SoC systems. In addition to its efficiency in terms of power, the scheme eliminates three types of crosstalk that cause miller-like transition on two or three adjacent wires simultaneously. The paper describes the technique, its implementation (using the widely adopted AMBA-AHB SoC bus standard) and provides experimental results indicating upto 38% energy saving for systems implemented in 0.18μm CMOS technology.
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© 2004 Springer-Verlag Berlin Heidelberg
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Khan, Z., Arslan, T., Erdogan, A.T. (2004). A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_60
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DOI: https://doi.org/10.1007/978-3-540-30205-6_60
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