Abstract
Due to the combination of flexibility and realization efficiency, reconfigurable hardware has become a promising implementation alternative. In the context of the IST-AMDREL project, a mixed granularity reconfigurable SoC platform targeting wireless communication systems has been developed. The platform’s main building blocks are presented, including coarse grain reconfigurable unit, embedded FPGA, interconnection network and application specific reusable blocks. The combination of these blocks in platform instances is expected to lead to a good balance between implementation efficiency and flexibility. An AMDREL platform based reconfigurable SoC for a multi-mode wireless networking system is currently under development.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Bartic, T.A., et al.: Highly Scalable Network on Chip for Reconfigurable Systems. In: International Symposium on System-on-Chip (SoC), Tampere, Finland (November 2003)
Marescaux, T., et al.: Networks on Chip as Hardware Components of an OS for Reconfigurable Systems. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, Springer, Heidelberg (2003)
Poon, K.K.W.: Power Estimation for Field-Programmable Gate Arrays. Master of Applied Science Dissertation, University of British Columbia (2002)
http://www.cbl.ncsu.edu/pub/Benchmark_dirs/LGSynth93/src/e2fmt/
Sentovich, M., et al.: SIS: A System for Sequential Circuit Synthesis. UCB/ERL M92/41 (1992)
Betz, V., Rose, J.: VPR: A New Packing, Placement and Routing Tool for FPGA Research. In: Glesner, M., Luk, W. (eds.) FPL 1997. LNCS, vol. 1304, pp. 213–222. Springer, Heidelberg (1997)
Duhamel, P., Hollomann, H.: Split Radix FFT Algorithm. Electronic Letters 20, 14–16 (1984)
Bricaud, P., Keating, M.: Reuse Methodology Manual for System-on-a-chip Designs. Kluwer Academic Publishers, Dordrecht (1999)
TondelayoTM 1 Baseband Product Brief. Systemonic, Inc. 100 Century Center Court, Suite 205 San Jose, CA 95112 USA
Thomson, J., et al.: An integrated 802.11a baseband and MAC processor. In: Digest of Technical Papers on Solid-State Circuits Conference 2002, vol. 2, pp. 92–93, 414–415 (2002)
Becker, J., et al.: DReAM: Dynamically Reconfigurable Architecture for future Mobile Commmunication applications. In: Grünbacher, H., Hartenstein, R.W. (eds.) FPL 2000. LNCS, vol. 1896, p. 312. Springer, Heidelberg (2000)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Masselos, K., Blionas, S., Mignolet, JY., Foster, A., Soudris, D., Nikolaidis, S. (2004). Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_63
Download citation
DOI: https://doi.org/10.1007/978-3-540-30205-6_63
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
Online ISBN: 978-3-540-30205-6
eBook Packages: Springer Book Archive