Abstract
An efficient logic transformation method to achieve both low power consumption and high testability is proposed in this paper. The proposed method is based on the redundancy insertion and removal approach. It is also described how redundant connections operate as test points in the test mode. The results of experiments on MCNC benchmark circuits show that the transformed circuit consumes less power in the normal mode and has higher testability in the test mode than the original.
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© 2004 Springer-Verlag Berlin Heidelberg
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Son, Y.S., Na, J.W. (2004). A New Logic Transformation Method for Both Low Power and High Testability. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_79
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DOI: https://doi.org/10.1007/978-3-540-30205-6_79
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
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