Abstract
Standby-power dissipation in ultra-deep submicron CMOS can be reduced by power switching. As the cut-off device has a strong impact on area consumption, minimum power-down time, signal delay and leakage suppression, a proper sizing of this device is of general importance. Therefore a two level compact simulation methodology is proposed which provides fast and accurate CAD support to the switch design task.
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Henzler, S., Georgakos, G., Berthold, J., Schmitt-Landsiedel, D. (2004). Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_81
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DOI: https://doi.org/10.1007/978-3-540-30205-6_81
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
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