Abstract
In this paper we present a model for delay and slew calculation in on chip bus structures respectively parallel routed wires. Capacitive coupling is often neglected during circuit design although it can have significant influence on the wire delay. The model takes capacitive coupling effects into account. It is based on interpreting the impulse response of a linear circuit as a probability distribution function. Closed-form equations are derived for length dependent moment calculations in integrated bus structures as well as for the effects on the wire delay and output slew. The model is suitable for performance evaluation and optimization.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Dartu, F., Pileggi, L.T.: CalculatingWorst-Case Delays Due to Dominant Capacitive Coupling. In: Proc. IEEE/ACM Design Automation Conference, pp. 46–51 (1997)
Tahedl, M., Pfleiderer, H.-J.: A Driver Load Model for Capacitive Coupled On-Chip Interconnect Busses. In: Proc. Int. Symposium on System-on-Chip, pp. 101–104 (2003)
O’Brien, P.R., Savarino, T.L.: Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation. In: Proc. IEEE Int. Conference on Computer-Aided Design, pp. 512–515 (1989)
Elmore, W.C.: The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers. Journal of Applied Physics 19, 55–63 (1948)
Alpert, C.J., Devgan, A., Kashyap, C.V.: RC Delay Metrics for Performance Optimization. IEEE Trans. on Computer-Aided Design 20, 571–582 (2001)
Alpert, C.J., Liu, F., Kashyap, C., Devgan, A.: Delay and Slew Metrics Using the Lognormal Distribution. In: Proc. IEEE/ACM Design Automation Conference, pp. 382–385 (2003)
Kashyap, C.V., Alpert, C.J., Liu, F., Devgan, A.: Closed Form Expressions for Extending Step Delay and Slew Metrics to Ramp Inputs. In: Proc. Int. Symposium on Physical Design, pp. 24–31 (2003)
Sato, T., Cao, Y., Agarwal, K., Sylvester, D., Hu, C.: Bidirectional Closed-Form Transformation Between On-Chip Coupling Noise Waveforms and Interconnect Delay-Change Curves. IEEE Trans. on Computer-Aided Design 22, 560–572 (2003)
Rosello, J.L., Segura, J.: A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. In: Proc. IEEE/ACM Design, Automation and Test in Europe (2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Tahedl, M., Pfleiderer, HJ. (2004). Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_9
Download citation
DOI: https://doi.org/10.1007/978-3-540-30205-6_9
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
Online ISBN: 978-3-540-30205-6
eBook Packages: Springer Book Archive