Abstract
Noise margin at read, at write and in stand-by is analyzed for the 6 transistor SRAM cell in a 0.18 μm process considering specific low power conditions such as low supply voltage and source-body biasing. These conditions reduce the noise margin. By using an asymmetrical cell design in which read is performed only on one of the two complementary bit lines, the noise margin can be improved and the bias limits extended for a reduced power consumption.
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Cserveny, S., Masgonty, J.M., Piguet, C. (2004). Noise Margin in Low Power SRAM Cells. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_91
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DOI: https://doi.org/10.1007/978-3-540-30205-6_91
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