Abstract
Late changes in silicon design (ECO) is a common although undesired practice. The need for ECO exists even in high-level design flows since bugs may occur in the specifications, in the compilation, or due to late specification changes. Esterel compilation deploys sequential optimization to improve delay and area of the netlist. This makes it harder to find in the netlist where manual changes should be done and to trace circuit changes back to the high-level specification. We show that all sequential optimizations used in Esterel compilation can be made reversible and demonstrate that an ECO problem can be reduced to a commonly solved combinational ECO problem. This is achieved by reconstructing some of the suppressed registers in order to backannotate to the original code. We demonstrate that the cost of reversibility is negligible.
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Arditi, L., Berry, G., Kishinevsky, M. (2004). Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs. In: Hu, A.J., Martin, A.K. (eds) Formal Methods in Computer-Aided Design. FMCAD 2004. Lecture Notes in Computer Science, vol 3312. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30494-4_10
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DOI: https://doi.org/10.1007/978-3-540-30494-4_10
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23738-9
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