Abstract
As an alternative way of chip design, Single Chip Multi-Processors (SCMP) has been a hot topic in microprocessor architecture research all the while. It achieves higher performance by extracting thread-level parallelism (TLP). Thread-level speculation (TLS) is an important way to simplify TLP extraction. This paper presents a new SCMP architecture called Griffon, which aims at general-purpose applications. It implements thread partition in assembly language. It supports thread-level speculation with simple logics and maintains data dependence using a dual-ring structure. Simulation and synthesis results show that Griffon can achieve ideal speedup, less design complexity and accessorial hardware cost.
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Lu, J., Zhang, C., Wang, Z., Cheng, Y., Wu, D. (2004). A Case of SCMP with TLS. In: Cao, J., Yang, L.T., Guo, M., Lau, F. (eds) Parallel and Distributed Processing and Applications. ISPA 2004. Lecture Notes in Computer Science, vol 3358. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30566-8_111
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DOI: https://doi.org/10.1007/978-3-540-30566-8_111
Publisher Name: Springer, Berlin, Heidelberg
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