Abstract
Designing a reliable and high performance multistage interconnection network (MIN) should consider the following issues carefully: (1) fault tolerance guarantee; (2) easy schemes and hardware design of rerouting switches; (3) low rerouting resulting in a low collision ratio. In this paper, we present the High Performance Chained Multistage Interconnection Network (HPCMIN) which has one-fault tolerance, destination tag routing for easy rerouting, one rerouting hop, resulting in a low collision ratio. From our simulation results, the HPCMIN results in a lower collision ratio than other dynamic rerouting networks. The HPCMIN is embedded with the indirect binary n-cube network(the ICube network) which is equivalent to many important MINs. Thus, the design methods used in the HPCMIN can be applied to these MINs so that they have the characteristics of the HPCMIN.
This research was supported by the National Science Council NSC-92-2213-E-324-006.
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© 2004 Springer-Verlag Berlin Heidelberg
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Chen, CW., Gan, PS., Chang, CH. (2004). Designing a High Performance and Fault Tolerant Multistage Interconnection Network with Easy Dynamic Rerouting. In: Cao, J., Yang, L.T., Guo, M., Lau, F. (eds) Parallel and Distributed Processing and Applications. ISPA 2004. Lecture Notes in Computer Science, vol 3358. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30566-8_114
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DOI: https://doi.org/10.1007/978-3-540-30566-8_114
Publisher Name: Springer, Berlin, Heidelberg
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