Abstract
In this paper, we present an OptimalProcessor Mapping (OPM) scheme to minimize data transmission cost for general BLOCK-CYCLIC data realignment. We examine a size oriented greedy matching method and the maximum bipartite matching theory to explore logical processor sequences. Based on these matching polices, the realigned sequences are used to perform data realignment in the destination phase. A significant improvement of our approach is that the OPM achieves high ratio of data remain in local space and leading minimum inter-processor communications. The OPM scheme could handle array realignment with arbitrary BLOCK-CYCLIC type and multidimensional arrays. Theoretical analysis and experimental results show that our technique provides considerable improvement for dynamic data realignment.
This work was supported in part by NSC of Taiwan under grant number NSC92-2213-E-216-025 and in part by Chung-Hua University, under contract CHU-93-TR-010.
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Hsu, CH., Yu, KM., Chen, CH., Yu, C.W., Lian, C.K. (2004). Optimal Processor Mapping Scheme for Efficient Communication of Data Realignment. In: Cao, J., Yang, L.T., Guo, M., Lau, F. (eds) Parallel and Distributed Processing and Applications. ISPA 2004. Lecture Notes in Computer Science, vol 3358. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30566-8_33
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DOI: https://doi.org/10.1007/978-3-540-30566-8_33
Publisher Name: Springer, Berlin, Heidelberg
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