Abstract
The increasing gap between processor and memory speeds is a well-known problem in modern computer architecture. Imagine stream architecture can solve bandwidth bottleneck by its particular memory hierarchy and stream processing for computationally intensive applications. Good performance has been demonstrated on media processing and partial scientific computing domains. Reed-Solomon (RS) codes are powerful block codes widely used as an error correction method. RS decoding demands a high memory bandwidth and intensive ALUs because of complex and special processing (galois field arithmetic), and real time requirement. People usually use specialized processor or DSP to solve it that gains high performance but lacks flexibility. This paper presents a software implementation of a parallel Reed-Solomon decoder on the Imagine platform. The implementation requires complex stream programming since the memory hierarchy and cluster organization of the underlying architecture are exposed to the Imagine programmer. Results demonstrate that Imagine has comparable performance to TI C64x. This work is an ongoing effort to validate the stream architecture is efficient and makes contribution to extend the application domain.
This work was supported by the 973 Project and the 863 Project(2001AA111050) of China.
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References
Shu Lin, D.J.C.: Error Control Coding Fundamentals and applications (1983)
Mattson, P., et al.: Imagine Programming System Developer’s Guide (2002), http://cva.stanford.edu
Beginner’s guide to Imagine Application Programming (March 2002), http://cva.stanford.edu
Imagine project, http://cva.stanford.edu/Imagine/project/
TI, Reed Solomon Decorder: TMS320C64x Implementation (2000)
ho Ahn, J., Dally, W.J., et al.: Evaluating the Imagine Stream Architecture. In: ISCA 2004 (2004)
Griem, G., Oliker, L.: Transitive Closure on the Imagine Stream Processor. In: 5th workshop on media and streaming processors, San Diego, CA (December 2003)
Wen, M., Wu, N., Li, H.-y., Zhang, C.: Multiple-dimension scalable adaptive stream architecture. In: Yew, P.-C., Xue, J. (eds.) ACSAC 2004. LNCS, vol. 3189, pp. 199–211. Springer, Heidelberg (2004)
Wu, N., Wen, M., et al.: Programming design patterns for the Imagine stream architecture. In: 13th National Conference on Information Storage Technology, Xi’an, China (2004)
Wen, M., Wu, N., et al.: Research of Stream Memory Hierarchy. In: 13th National Conference on Information Storage Technology, Xi’an, China (2004)
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Wen, M., Zhang, C., Wu, N., Li, H., Li, L. (2004). A Parallel Reed-Solomon Decoder on the Imagine Stream Processor. In: Cao, J., Yang, L.T., Guo, M., Lau, F. (eds) Parallel and Distributed Processing and Applications. ISPA 2004. Lecture Notes in Computer Science, vol 3358. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30566-8_6
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DOI: https://doi.org/10.1007/978-3-540-30566-8_6
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