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System-on-Chip Verification Process Using UML

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Book cover UML Modeling Languages and Applications (UML 2004)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 3297))

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Abstract

In this paper, we propose a verification methodology for System-On-Chip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze and formalize the specification. The specification and implementation validation can be performed systematically by introducing UML. We applied our method to a Mobile Media Processors SoC. We improved the quality of ΞΆ the specification written in informal natural language through UML modeling techniques. The test scenarios and coverage metrics for implementation are derived from the UML model systematically. The result shows that our proposal is effective for eliminating errors from both specification and implementation.

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Zhu, Q., Nakata, T., Mine, M., Kuroki, K., Endo, Y., Hasegawa, T. (2005). System-on-Chip Verification Process Using UML. In: Jardim Nunes, N., Selic, B., Rodrigues da Silva, A., Toval Alvarez, A. (eds) UML Modeling Languages and Applications. UML 2004. Lecture Notes in Computer Science, vol 3297. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-31797-5_15

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  • DOI: https://doi.org/10.1007/978-3-540-31797-5_15

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-25081-4

  • Online ISBN: 978-3-540-31797-5

  • eBook Packages: Computer ScienceComputer Science (R0)

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