Abstract
The resistance of on-chip interconnects and the current drive of transistors is strongly temperature dependent. As a result, the interconnect performance is affected by the temperature in a sizeable proportion. In this paper we evaluate thermal effects in global RLC interconnects and quantify their impact in a standard optimization procedure in which repeaters are used. By evaluating the difference between a simple RC and an accurate RLC model, we show how the temperature induced increase of resistance may reduce the impact of inductance. We also project the evolution of such effects in future technology nodes, according to the semiconductor roadmap.
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© 2003 Springer-Verlag Berlin Heidelberg
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Casu, M.R., Graziano, M., Piccinini, G., Masera, G., Zamboni, M. (2003). Effects of Temperature in Deep-Submicron Global Interconnect Optimization. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_11
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DOI: https://doi.org/10.1007/978-3-540-39762-5_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20074-1
Online ISBN: 978-3-540-39762-5
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