Abstract
Stand-by power reduction for storage circuits, which have to retain data, is obtained through limited locally switched source-body biasing. The stand-by leakage current is reduced by using a source-body bias not exceeding the value that guaranties safe data retention and less leaking non-minimum length transistors. This bias is short-circuited in active mode to improve the speed and the noise margin, especially for low supply voltages; however, this is made for a fraction of the circuit containing the activated part, allowing a trade-off between switching power and leakage. For a SRAM in a 0.18μm process the leakage is reduced more than 25 times without speed or noise margin loss.
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Cserveny, S., Masgonty, J.M., Piguet, C. (2003). Stand-by Power Reduction for Storage Circuits. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_29
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DOI: https://doi.org/10.1007/978-3-540-39762-5_29
Publisher Name: Springer, Berlin, Heidelberg
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