Abstract
A methodology for the power-efficient implementation of multimedia kernels based on reconfigurable hardware (FPGA) is introduced. The methodology combines various types of algorithmic transformations and high-level memory hierarchy exploration with register-transfer level design and implementation. An FPGA with an external memory was used for obtaining experimental results which prove the viability of the methodology. Comparisons among implementations with and without this optimization, prove that great power efficiency is achieved.
This work was partially supported by the project IST-34793-AMDREL which is funded by the E.C.
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Tatas, K. et al. (2003). Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_49
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DOI: https://doi.org/10.1007/978-3-540-39762-5_49
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