Abstract
Design approaches, which take into account signal statistics, show good results with respect to power optimization. Since HDL coding and verification by RTL simulation is the preferred flow in the design of SoCs, this level of design abstraction comprises a high potential for low-power digital design. In this paper an approach is presented, how calculation of RTL signal statistics can be accomplished and which types of on-line statistics can be calculated efficiently. With two small examples it is furthermore shown, how the knowledge about signal statistics can be exploited for low-power design approaches.
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Fugger, P. (2003). RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_62
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DOI: https://doi.org/10.1007/978-3-540-39762-5_62
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20074-1
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