Abstract
An approach of intelligent retargetable tuneable compiler is introduced to overcome the gap between hardware and software development and to increase performance of embedded systems by enhancing their instruction-level-parallelism. It focuses on high-level model and knowledgeable treatment of code generation where knowledge about target microprocessor architecture and human-level heuristics are integrated into compiler production expert system. XML is used as platform-independent representation of data and knowledge for design process. Structure of an experimental compiler which is developed to support the approach for microprocessors with irregular architecture like DSP and VLIW-DSP is described. A technique to detect optimal processor architecture and instruction-level-parallelism for program execution is presented. Results of code generation experiments are presented for DSPstone benchmarks.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Marwedel, P., Goossens, G.: Code Generation for Embedded Processors. Kluwer Academic Publishers, Dordrecht (1995)
Hadjiyiannis, G., Hanono, S., Devadas, S.: ISDL: An Instruction Set Description Language for Retargetability. In: Proc. 34th Design Automation Conference, pp. 299–302. ACM Press, New York (1997)
Marwedel, P.: The MIMOLA Design System: Tools for Design of Digital Processors. In: Proc. 21th Design Automation Conference, pp. 587–593. ACM Press, New York (1984)
Leupers, R.: Retargetable Code Generation for Digital Signal Processors. Kluwer Academic Publishers, Dordrecht (1997)
Liem, C., Paulin, P.: FlexWare - a Flexible Firmware Development Environment. In: Proc. European Design and Test Conference, pp. 31–37. ACM Press, New York (1994)
Fauth, A., Praet, J.V., Freericks, M.: Describing Instruction Set Processors Using nML. In: Proc. European Design and Test Conference, March 1995, pp. 503–507. ACM Press, Paris (1995)
Bashford, S.: Code Generation Techniques for Irregular Architectures. Tech. Rep. 596, Universitat Dortmund (1995)
Fisher, R.J., Dietz, H.G.: The Sec compiler: SWARing at MMX and 3Dnow! In: Annual WS on Lang, and Compilers for Parallel Computing. ACM Press, New York (1999)
Steinke, S., Schwarz, R., Wehmeyer, L., Marwedel, P.: Low power code generation for a RISC processor by Register Pipelining. Technical Report 754, University of Dortmund, Dept. of Computer Science XII (2001)
Leupers, R., Kotte, D.: Variable Partitioning for dual memory banks DSPs. In: ICASSP, Salt Lake City, USA), May 2001. ACM Press, New York (2001)
Ragozin, D.V.: Retargetable code generation methods for irregular long instruction word microprocessor architectures. PhD thesis. Institute of Software Systems, National Academy of Sciences of Ukraine, Kiev (2002) (in ukrainian)
Aho, A.V., Sethi, R., Ullman, J.D.: Compilers: Principles, Techniques and Tools. Addison-Wesley, Reading (1986)
Stallman, R.: Using and Porting the GNU Compiler Collection. Addison-Wesley Publishing, New York (2000)
Michie, D. (ed.): Expert Systems in the Microelectronic age. Edinburgh University Press (1979)
Doroshenko, A.Y., Kuivashev (Ragozin), D.V.: Intelligent compacting compilers for VLIW microprocessors. Problems of Programming, N°l-2, 138-151 (2001) (in ukrainian)
Leary, K.: Waddington. W.: DSP-C. A Standard High Level Language for DSP and Numeric Processing. In: Proc. of ICASSP-90, April 1990, pp. 1065–1068. ACM Press, New York (1990)
Saghir, M., Chow, P., Lee, C.: Exploiting Dual Data-Memory Banks in Digital Signal Processors. In: Proc. of 8fh Int. Conf. on Architectural Support for Programming Languages and Operation Systems, pp. 234–243. ACM Press, New York (1996)
Ebcioglu, K., Nakatani, T.: A New Compilation Technique for Parallelizing Loops with Unpredictable Branches on a VLIW Architecture. In: Languages and Compilers for Parallel Computer, pp. 213–229. MIT Press, Cambridge (1990)
Zivojnovic, V., Schraut, F.L., Willems, M., Schoenen, R.: DSPs, GPPs, and Multimedia Applications - an Evaluation Using DSPstone. In: Proc. Int. Conf. on Signal Processing Applications and Technology, Boston, Mass. DSP Associates, pp. 1779–1783 (1995)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Doroshenko, A., Ragozin, D. (2003). Retargetable and Tuneable Code Generation for High Performance DSP. In: Malyshkin, V.E. (eds) Parallel Computing Technologies. PaCT 2003. Lecture Notes in Computer Science, vol 2763. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45145-7_42
Download citation
DOI: https://doi.org/10.1007/978-3-540-45145-7_42
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40673-0
Online ISBN: 978-3-540-45145-7
eBook Packages: Springer Book Archive