Abstract
Future processors having sliced memory pipelines will rely on bank prediction to schedule memory instructions to a first-level cache split into banks. In a deeply pipelined processor, even a small bank misprediction rate may degrade performance severely. The goal of this paper is to counteract the bank misprediction penalty, so that in spite of such bank misprediction, performance suffers little. Our contribution is twofold: a new recovery scheme for latency misprediction, and two policies for selectively replicating loads to all banks. The proposals have been evaluated for 4 and 8-way superscalar processors and a wide range of pipeline depths. The best combination of our mechanisms improves IPC of an 8-way baseline processor up to 11%, removing up to two thirds of the bank misprediction penalty.
This work was supported in part by the Ministry of Education of Spain under grant TIC 2001-0995-C02-02 and the Diputación General de Aragón (BOA 58,14/05/03).
Chapter PDF
Similar content being viewed by others
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
Agarwal, V., et al.: Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures. In: Proc. of 27th ISCA, pp. 248–259 (2000)
Borch, E., Tune, E., Manne, S., Emer, J.: Loose Loops Sink Chips. In: Proc. of 8th HPCA, pp. 299–310 (2002)
Burger, D.C., Austin, T.M.: The SimpleScalar Tool Set, Version 2.0. UW Madison Computer Science Technical Report #1342 (1997)
Case, B.: Intel Reveals Pentium Implementation Details. MPR 7(4), 1–9 (1993)
Cho, S., Yew, P., Lee, G.: A High-Bandwidth Memory Pipeline for Wide Issue Processors. IEEE Trans. on Computers 50(7), 709–723 (2001)
Cortadella, J., Llabería, J.M.: Evaluation of A+B=K Conditions without Carry Propagation. IEEE Trans. on Computers 41(11), 1484–1488 (1992)
Edmondson, J., Rubinfeld, P., Rajagopalan, V.: Superscalar Instruction Execution in the 21164 Alpha Microprocessor. IEEE Micro 15(2), 33–43 (1995)
Farrell, J.A., Fisher, T.C.: Issue Logic for a 600 Mhz Out-of-Order Execution Microprocessor. IEEE J. of Solid-State Circuits 33(5), 707–712 (1998)
Gwennap, L.: IBM Regains Performance Lead with Power2. MPR 7(13) (1993)
Hinton, G., et al.: The Microarchitecture of the Pentium 4 Processor. ITJ Q1 (2001)
Hsu, P.: Design of the R8000 Microprocessor. IEEE Micro 14, 23–33 (1994)
Kessler, R.: The Alpha 21264 Microprocessor. IEEE Micro 19(2), 24–36 (1999)
Kumar, A.: The HP PA-8000 RISC CPU. IEEE Micro 17(2), 27–32 (1997)
Matson, M., et al.: Circuit Implementation of a 600MHz Superscalar RISC Microprocessor. In: Proc. of ICCD, pp. 104–110 (1998)
Michaud, P., Seznec, A., Uhlig, R.: Trading Conflict and Capacity Aliasing in Conditional Branch Predictors. In: Proc. of 24th ISCA, pp. 292–303 (1997)
Morancho, E., LLabería, J.M., Olivé, A.: Recovery Mechanism for Latency Misprediction. In: Proc. of PACT, pp. 118–128 (2001)
Naffziger, S., et al.: The implementation of the Itanium 2 Microprocessor. IEEE J. Solid State Circuits 37(11), 1448–1460 (2002)
Neefs, H., Vandierendonck, H., De Bosschere, K.: A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks. In: Proc. of 6th HPCA, pp. 313–324 (2000)
Seznec, A., Felix, S., Krishnan, V., Sazeides, Y.: Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor. In: Proc. of 29th ISCA, pp. 295–306 (2002)
Sherwood, T., Perelman, E., Hamerly, G., Calder, B.: Automatically Characterizing Large Scale Program Behaviour. In: Proc. of ASPLOS (2002)
Sohi, G.S., Franklin, M.: High-Bandwidth Memory Systems for Superscalar Processors. In: Proc. 4th ASPLOS, pp. 53–62 (1991)
Yoaz, A., Mattan, E., Ronen, R., Jourdan, S.: Speculation Techniques for Improving Load Related Instruction Scheduling. In: Proc. of 26th ISCA, pp. 42–53 (1999)
Zyuban, V., Kogge, P.M.: Inherently Lower-Power High-Performance Superscalar Architectures. IEEE Trans. on Computers 50(3), 268–285 (2001)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Torres, E.F., Ibañez, P., Viñals, V., Llabería, J.M. (2003). Counteracting Bank Misprediction in Sliced First-Level Caches. In: Kosch, H., Böszörményi, L., Hellwagner, H. (eds) Euro-Par 2003 Parallel Processing. Euro-Par 2003. Lecture Notes in Computer Science, vol 2790. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45209-6_83
Download citation
DOI: https://doi.org/10.1007/978-3-540-45209-6_83
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40788-1
Online ISBN: 978-3-540-45209-6
eBook Packages: Springer Book Archive