Abstract
This paper presents the residue number system (RNS) implementation of reduced complexity and high performance adaptive FIR filters on Altera APEX20K field-programmable logic (FPL) devices. Index arithmetic over Galois fields along with a selection of a small wordwidth modulus set are keys for attaining low-complexity and high-throughput. The replacement of a classical modulo adder tree by a binary adder with extended precision followed by a single modulo reduction stage improved area requirements by 10% for a 32-tap FIR filter. A block LMS (BLMS) implementation was preferred for the update of the adaptive FIR filter coefficients. RNS-FPL merged filters demonstrated its superiority when compared to 2C (two’s complement) filters, being about 65% faster and requiring fewer logic elements for most study cases.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Szabo, N.S., Tanaka, R.I.: Residue Arithmetic and its Applications to Computer Technology. McGraw-Hill, New York (1967)
Soderstrand, M., Jenkins, W., Jullien, G.A., Taylor, F.J.: Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. IEEE Computer Society Press, Los Alamitos (1986)
Ramírez, J., Meyer-Bäse, U., Taylor, F., García, A., Lloris, A.: Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies. Journal of VLSI Signal Processing 34, 227–237 (2003)
Ramírez, J., García, A., Meyer-Bäse, U., Lloris, A.: Fast RNS-based FPL Communications Receiver Design and Implementation. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 472–481. Springer, Heidelberg (2002)
Hamann, V., Sprachmann, M.: Fast Residual Arithmetic with FPGAs. In: Workshop on Design Methodologies for Microelectronics (1995)
Safiri, H., Ahamadi, H., Jullien, G., Dimitrov, V.: Design of FPGA Implementation of Systolic FIR Filters Using Fermat Number ALU. In: Asilomar Conference on Signals, Systems and Computers, Pacific Grove (1997)
Meyer-Bäse, U., García, A., Taylor, F.: Implementation of a Communications Channelizer Using FPGAs and RNS Arithmetic. Journal of VLSI Signal Processing 28(1/2), 115–128 (2001)
Jenkins, W.K., Schnaufer, B.A.: Fault tolerant adaptive filters based on the block LMS algorithm. 1993 IEEE International Symposium on Circuits and Systems 1, 862–865 (1993)
Liu, C.M., Jen, C.W.: A parallel adaptive algorithm for moving target detection and its VLSI array realization. IEEE Transactions on Signal Processing 40(11), 2841–2848 (1992)
Griffin, M., Sousa, M., Taylor, F.: Efficient Scaling in the Residue Number System. In: 1989 International Conference on Acoustics, Speech and Signal Processing, pp. 1075–1078 (1989)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Ramírez, J., Meyer-Bäse, U., García, A., Lloris, A. (2003). Design and Implementation of RNS-Based Adaptive Filters. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_138
Download citation
DOI: https://doi.org/10.1007/978-3-540-45234-8_138
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40822-2
Online ISBN: 978-3-540-45234-8
eBook Packages: Springer Book Archive