Abstract
This paper introduces new scheduling and allocation algorithms for designing with hybrid arithmetic component libraries composed of both operation-specific components and flexible components capable of executing multiple operations. The flexible components are implemented primarily in fixedlogic with only small amounts of application-specific reconfigurability, which provides the flexibility needed without the negative area and performance penalties commonly associated with general-purpose reconfigurable arrays. Results obtained with hybrid library scheduling and allocation on a variety of digital signal processing (DSP) filters reveal that significant area savings are achieved.
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© 2003 Springer-Verlag Berlin Heidelberg
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Kumar, V.V., Lach, J. (2003). Designing, Scheduling, and Allocating Flexible Arithmetic Components. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_145
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DOI: https://doi.org/10.1007/978-3-540-45234-8_145
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Print ISBN: 978-3-540-40822-2
Online ISBN: 978-3-540-45234-8
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