Abstract
In this paper we propose a design space exploration method targeting reconfigurable architectures that takes place at the algorithmic level and aims to rapidly highlight architectures that present good performance vs. flexibility tradeoffs. The exploration flow is based on a functional model to describe the architectures that the designer wants to compare. The paper mainly focuses on the projection step of our flow and presents an allocation heuristic that is based on communication costs reduction.
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Hartenstein, R.: A Decade of Reconfigurable Computing: a Visionary Retrospective. In: DATE 2001, Munich, Germany, March 13-16 (2001)
Rabaey, J.M.: Reconfigurable Processing: The Solution to Low-Power Programmable DSP. In: IEEE, ICASSP 1997, Munich, Germany (April 1997)
Betz, V., Rose, J., Marquart, A.: Architecture and CAD for Deep Submicron FPGAs. Kluwer Academic Publishers, Dordrecht (1999)
Lagadec, L., Lavenier, D., Fabiani, E., Pottier, B.: Placing, Routing and Editing Virtual FPGAs. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, p. 357. Springer, Heidelberg (2001)
Nageldinger, U.: Coarse-Grained Reconfigurable Architecture Design Space exploration. Ph.D. Thesis, University of Kaiserlautern, Germany (June 2001)
Moritz, C.A., Yeung, D., Agarwal, A.: Exploring Optimal Cost-Performance designs for Raw Microprocessors. In: FCCM 1998, Napa, CA, USA (April 1998)
Bossuet, L., Gogniat, G., Diguet, J.P., Philippe, J.L.: A Modeling Method for Reconfigurable Architecture. In: IWSOC 2002, Banff, Canada (July 2002)
Le Moullec, Y., Diguet, J.P., Philippe, J.L.: Design Trotter: a Multimedia Embedded Systems Design Space Exploration Tool. In: IEEE MMSP 2002, Virgin Island, USA, December 9-11 (2002)
Le Moullec, Y., Ben Amor, N., Diguet, J.P., Abid, M., Philippe, J.L.: Multi-Granularity Metrics for the Era of Strongly Personalized SOCs. In: DATE 2003, Munich, Germany, March 3-7 (2003)
Diguet, J.P., Gogniat, G., Danielo, P., Auguin, M., Philippe, J.L.: The SPF model. In: FDL 2000, Tübingen, Germany (September 2000)
Bossuet, L., Burleson, W., Gogniat, G., Anand, V., Laffely, A., Philippe, J.L.: Targeting Tiled Architectures in Design Exploration. In: RAW 2003, Nice, France (April 2003)
Budiu, M., Goldstein, S.C.: Fast Compilation for PipeRench Reconfigurable fabrics. In: ACM/SIGDA FPGA 1999, Monterey, CA, USA (February 1999)
Shang, L., Kaviani, A., Bahala, K.: Dynamic Power in VirtexTM-II FPGA Family. In: ACM/SIGDA FPGA 2002, Monterey, Californie, USA (February 2002)
Garcia, A., Burleson, W., Danger, J.L.: Power Modeling in Field Programmable Gate Arrays (FPGA). In: Lysaght, P., Irvine, J., Hartenstein, R.W. (eds.) FPL 1999. LNCS, vol. 1673, pp. 396–404. Springer, Heidelberg (1999)
Zhang, H., Wan, M., George, V., Rabaey, J.: Interconnect Architecture Exploration for Low-Energy Reconfigurable Single-Chip DSPs. IEEE Computer Society Workshop on VLSI (April 1999)
Bhaskaran, V., Konstantinides, K.: Image and Video Compression Standards: Algorithms and Architectures. Kluwer Academic Publishers, Dordrecht (1995)
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Bossuet, L., Gogniat, G., Philippe, JL. (2003). Communication Costs Driven Design Space Exploration for Reconfigurable Architectures. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_89
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DOI: https://doi.org/10.1007/978-3-540-45234-8_89
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