Skip to main content
SpringerLink
Log in
Book cover

International Conference on Field Programmable Logic and Applications

FPL 2003: Field Programmable Logic and Application pp 952–955Cite as

Adaptive Processor: A Dynamically Reconfiguration Technology for Stream Processing

  • Conference paper
  • First Online:

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2778))

Abstract

In order to improve the performance of reconfigurable computing, the number of reconfigurable units is increased with advance of semiconductor technology. The array of reconfigurable units can be configured to application-specific pipelined processing datapath. Then configuration overhead will be critical overhead of total execution time for dynamic reconfiguration based system. In this paper, models of efficient configuration methodology and application-specific pipelined stream processing are proposed. Adaptive processor architecture is also proposed, and discussed in summary.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Holt, R.C.: Some Deadlock Properties of Computer Systems. Computing Surveys 4(3), 179–196 (1972)

    Article  MathSciNet  Google Scholar 

  2. Wirthin, M.J., Hutchings, B.L.: DISC: The dynamic instruction set computer, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing. In: Proc. SPIE 2607, pp. 92–103 (1995)

    Google Scholar 

  3. Mattson, R.L., Gecsei, J., Slutz, D.R., Trainger, I.L.: Evaluation techniques for storage hierarchies. IBM Systems Journal 9(2), 78–117 (1970)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Graduate School of Computer Science and Engineering, University of Aizu, 965-8580, Aizu-Wakamatsu, Fukushima-ken, Japan

    Shigeyuki Takano

Authors
  1. Shigeyuki Takano
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Department of Electrical and Electronic Engineering, Imperial College London, Exhibition Road, SW7 2BT, London, UK

    Peter Y. K. Cheung

  2. Department of Electrical & Electronic Engineering, Imperial College London, Exhibition Road, SW7 2BT, London, UK

    George A. Constantinides

Rights and permissions

Reprints and permissions

Copyright information

© 2003 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Takano, S. (2003). Adaptive Processor: A Dynamically Reconfiguration Technology for Stream Processing. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_93

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-45234-8_93

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-40822-2

  • Online ISBN: 978-3-540-45234-8

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation