Abstract
Field programmable gate array based reconfigurable computing machines have successfully demonstrated their performance advantages for a large class of compute intense problems. In this paper, we present a partially and dynamically reconfigurable architecture, NEBULA, which reduces the inherent overheads of reconfigurable computing. NEBULA is built around Xilinx 6200 family of devices. NEBULA is supported by a collection of drivers and CAE tools that allow rapid implementation of algorithms in the reconfigurable core. We also present experimental results that highlight the performance capabilities of NEBULA. With very small reconfiguration and communication overhead, we are able to use NEBULA to speed up a large class of applications.
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© 1999 Springer-Verlag Berlin Heidelberg
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Bhatia, D., Simha, K.S., Kannan, P. (1999). NEBULA: A Partially and Dynamically Reconfigurable Architecture. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_45
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DOI: https://doi.org/10.1007/978-3-540-48302-1_45
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66457-4
Online ISBN: 978-3-540-48302-1
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