Abstract
Model checking is emerging as a practical tool for detecting logical errors in early stages of system design. We investigate the model checking of hierarchical (nested) systems, i.e. finite state machines whose states themselves can be other machines. This nesting ability is common in various software design methodologies and is available in several commercial modeling tools. The straightforward way to analyze a hierarchical machine is to flatten it (thus, incurring an exponential blow up) and apply a model checking tool on the resulting ordinary FSM.
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Alur, R., Yannakakis, M.: Model checking of hierarchical state machines. In: Proceedings of the Sixth ACM SIGSOFT Symposium on Foundations of Software Engineering (November 1998)
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© 1998 Springer-Verlag Berlin Heidelberg
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Alur, R. (1998). Efficient Formal Verification of Hierarchical Descriptions. In: Arvind, V., Ramanujam, S. (eds) Foundations of Software Technology and Theoretical Computer Science. FSTTCS 1998. Lecture Notes in Computer Science, vol 1530. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-49382-2_24
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DOI: https://doi.org/10.1007/978-3-540-49382-2_24
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