Abstract
In this paper, we examine the trade-offs in performance and area due to customizing the datapath and instruction set architecture of a soft VLIW processor implemented in a high-density FPGA. In addition to describing our processor, we describe a number of microarchitectural optimizations we used to reduce the area of the datapath. We also describe the tools we developed to customize, generate, and program our processor. Our experimental results show that datapath and instruction set customization achieve high levels of performance, and that using on-chip resources and implementing microarchitectural optimizations like selective data forwarding help keep FPGA resource utilization in check.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer Berlin Heidelberg
About this paper
Cite this paper
Saghir, M.A.R., El-Majzoub, M., Akl, P. (2007). Customizing the Datapath and ISA of Soft VLIW Processors. In: De Bosschere, K., Kaeli, D., Stenström, P., Whalley, D., Ungerer, T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2007. Lecture Notes in Computer Science, vol 4367. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-69338-3_19
Download citation
DOI: https://doi.org/10.1007/978-3-540-69338-3_19
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-69337-6
Online ISBN: 978-3-540-69338-3
eBook Packages: Computer ScienceComputer Science (R0)