Abstract
Nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowires has been predicted to be an alternative to silicon technology since lithography based IC is approaching its limit in terms of feature size. However, such processes are expected to be less reliable, to have high defect density and to be handled with effective defect tolerant techniques. Thus, reliability is a major challenge in the future of IC design. To this end, different coding techniques have been proposed to improve reliability of future technologies. In this paper we analyze the trade-off between the area and the reliability added in each chip employing the Reed Muller coding as the coding technique. We estimate the reliability and area increase of different orders of the Reed Muller decoding and observed that while the area increases, the reliability decreases. Our approach is to define a framework and help designers in order to decide on the configuration of the Reed Muller to be used. Finally, we provide a guideline to optimize the architecture making an optimal trade off between the area and the reliability.
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Argyrides, C., Loizidou, S., Pradhan, D.K. (2008). Area Reliability Trade-Off in Improved Reed Muller Coding. In: Bereković, M., Dimopoulos, N., Wong, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2008. Lecture Notes in Computer Science, vol 5114. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-70550-5_13
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DOI: https://doi.org/10.1007/978-3-540-70550-5_13
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-70549-9
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