Abstract
This paper focuses on the instruction fetch resources in a real-time SMT processor to provide an energy-efficient configuration for a soft real-time application running as a high priority thread as fast as possible while still offering decent progress in low priority or non-real-time thread(s). We propose a fetch mechanism, Fetch-around, where a high priority thread accesses the L1 ICache, and low priority threads directly access the L2. This allows both the high and low priority threads to simultaneously fetch instructions, while preventing the low priority threads from thrashing the high priority thread’s ICache data. Overall, we show an energy-performance metric that is 13% better than the next best policy when the high performance thread priority is 10x that of the low performance thread.
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References
Tullsen, D., Eggers, S.J., Levy, H.M.: Simultaneous multithreading: Maximizing on-chip parallelism. In: Proceedings of the 22nd Annual Intl. Symposium on Computer Architecture (June 1995)
Brandt, S., Nutt, G., Berk, T., Humphrey, M.: Soft real-time application execution with dynamic quality of service assurance. In: Proceedings of the 6th IEEE/IFIP International Workshop on Quality of Service (May 1998)
Raasch, S.E., Reinhardt, S.K.: Applications of thread prioritization in smt processors. In: Proceedings of Multithreaded Execution, Architecture and Compilation Workshop (January 1999)
Dorai, G.K., Yeung, D.: Transparent threads: Resource sharing in smt processors for high single-thread performance. In: Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (2002)
Yamasaki, N.: Responsive multithreaded processor for distributed real-time processing. Journal of Robotics and Mechatronics, 44–56 (2006)
Falcón, A., Ramirez, A., Valero, M.: A low-complexity, high-performance fetch unit for simultaneous multithreading processors. In: Proceedings of the 10th Intl. Conference on High Performance Computer Architecture (February 2004)
Klauser, A., Grunwald, D.: Instruction fetch mechanisms for multipath execution processors. In: Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture (November 1999)
Burns, J., Gaudiot, J.L.: Quantifying the smt layout overhead, does smt pull its weight? In: Proc. Sixth Int’l Symp. High Performance Computer Architecture (HPCA) (January 2000)
Suh, G., Devadas, S., Rudolph, L.: Dynamic cache partitioning for simultaneous multithreading systems. In: The 13th International Conference on Parallel and Distributed Computing System (PDCS) (August 2001)
Tullsen, D.M., Eggers, S.J., Emer, J.S., Levy, H.M., Lo, J.L., Stamm, R.L.: Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor. In: Proceedings of the 23rd Annual International Symposium on Computer Architecture (ISCA) (May 1996)
El-Moursy, A., Albonesi, D.H.: Front-end policies for improved issue efficiency in smt processors. In: Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA) (February 2003)
Cazorla, F.J., Knijnenburg, P.M., Sakellariou, R., Fernández, E., Ramirez, A., Valero, M.: Predictable performance in smt processors. In: Proceedings of the 1st Conference on Computing Frontiers (April 2004)
Yamasaki, N., Magaki, I., Itou, T.: Prioritized smt architecture with ipc control method for real-time processing. In: 13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS 2007), pp. 12–21 (2007)
Jain, R., Hughes, C.J., Adve, S.V.: Soft real-time scheduling on simultaneous multithreaded processors. In: Proceedings of the 23rd IEEE Real-Time Systems Symposium (December 2002)
El-Haj-Mahmoud, A., AL-Zawawi, A.S., Anantaraman, A., Rotenberg, E.: Virtual multiprocessor: An analyzable, high-performance microarchitecture for real-time computing. In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2005) (September 2005)
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Özer, E., Dreslinski, R.G., Mudge, T., Biles, S., Flautner, K. (2008). Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor. In: Bereković, M., Dimopoulos, N., Wong, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2008. Lecture Notes in Computer Science, vol 5114. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-70550-5_3
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DOI: https://doi.org/10.1007/978-3-540-70550-5_3
Publisher Name: Springer, Berlin, Heidelberg
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