Abstract
This paper aims at comparing multiplication algorithms over \(\mathbb{F}_{{p}^{m}}\)on FPGA. Contrary to previous surveys providing the reader with an estimate of both area and delay in terms of XOR gates, we discuss place-and-route results which point out that the choice of an algorithm depends on the irreducible polynomial and on some architectural parameters. We designed a VHDL code generator to easily study a wide range of algorithms and parameters.
This work was supported by the New Energy and Industrial Technology Development Organization (NEDO), Japan.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Barreto, P.S.L.M.: A note on efficient computation of cube roots in characteristic 3. Cryptology ePrint Archive, Report 2004/305 (2004)
Bertoni, G., et al.: Efficient GF(p m) arithmetic architectures for cryptographic applications. In: Joye, M. (ed.) CT-RSA 2003. LNCS, vol. 2612, pp. 158–175. Springer, Heidelberg (2003)
Beuchat, J.-L., et al.: An algorithm for the η T pairing calculation in characteristic three and its hardware implementation. Cryptology ePrint Archive, Report 2006/327 (2006)
Erdem, S.E., Yamk, T., Koç, Ç.K.: Polynomial basis multiplication over GF(2m). Acta Applicandae Mathematicae 93(1–3), 33–55 (2006)
Grabher, P., Page, D.: Hardware acceleration of the Tate Pairing in characteristic three. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 398–411. Springer, Heidelberg (2005)
Guajardo, J., et al.: Efficient hardware implementation of finite fields with applications to cryptography. Acta Applicandae Mathematicae 93(1–3), 75–118 (2006)
Kerins, T., et al.: Efficient hardware for the Tate Pairing calculation in characteristic three. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 412–426. Springer, Heidelberg (2005)
Kerins, T., Popovici, E., Marnane, W.: Algorithms and architectures for use in FPGA implementations of identity based encryption schemes. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, vol. 3203, pp. 74–83. Springer, Heidelberg (2004)
Kumar, S., Wollinger, T., Paar, C.: Optimum digit serial GF(2m) multipliers for curve-based cryptography. IEEE Transactions on Computers 55(10), 1306–1311 (2006)
Ronan, R., et al.: An embedded processor for a pairing-based cryptosystem. In: Proceedings of the Third International Conference on Information Technology: New Generations (ITNG’06), IEEE Computer Society Press, Los Alamitos (2006)
Shu, C., Kwon, S., Gaj, K.: FPGA accelerated Tate pairing based cryptosystem over binary fields. Cryptology ePrint Archive, Report 2006/179 (2006)
Song, L., Parhi, K.K.: Low energy digit-serial/parallel finite field multipliers. Journal of VLSI Signal Processing 19(2), 149–166 (1998)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer Berlin Heidelberg
About this paper
Cite this paper
Beuchat, JL., Miyoshi, T., Oyama, Y., Okamoto, E. (2007). Multiplication over \(\mathbb{F}_{{p}^{m}}\) on FPGA: A Survey. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2007. Lecture Notes in Computer Science, vol 4419. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71431-6_20
Download citation
DOI: https://doi.org/10.1007/978-3-540-71431-6_20
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-71430-9
Online ISBN: 978-3-540-71431-6
eBook Packages: Computer ScienceComputer Science (R0)