Abstract
We present a method for implementing a fast multiplier for finite fields GF(2m) generated by irreducible trinomials of the form α m + α n + 1. We propose a design based on the Mastrovito multiplier which is described by a parallel/serial architecture that computes a multiplication in m clock cycles by using only bit-adders (XORs), bit-multipliers (ANDs), and shift registers. This approach exploits symmetries and subexpression sharing in Mastrovito matrices in order to reduce the number of operations, and hence computation time in our FPGA implementation. According to preliminary performance results, our approach performs efficiently for large fields and has potential for a variety of applications, such as cryptography, coding theory, and the reverse engineering problem for genetic networks.
This research is supported by grant NIH-MBRS (SCORE) S06-GM08102.
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Ferrer, E., Bollman, D., Moreno, O. (2007). A Fast Finite Field Multiplier. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2007. Lecture Notes in Computer Science, vol 4419. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71431-6_22
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DOI: https://doi.org/10.1007/978-3-540-71431-6_22
Publisher Name: Springer, Berlin, Heidelberg
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